The function of chip failure analysis is to locate the failure point of abnormal chips (signal detection errors) and determine the mechanism of chip failure based on the original design of the chip. Conducting failure analysis requires comprehensive knowledge, covering many aspects such as electronics, technology, structure, materials, physics and chemistry. Test items: Chip failure analysis IC Integrated circuit failure analysis: Open package, 3D-OM, C-SAM/SAT, 2DX-Ray, 3DX-Ray, SEM-EDX, OBIRCH/EMMI, RIE, Nanoprobe, ESD (HBM, MM, Latch up), AFM, SIMS, TOF-SIMS, TEM, XPS, I-V, C-V Test range: Integrated circuit, chip detection standard: GJB 548B-2005 Chip failure analysis method: 01.OM microscope observation, Appearance analysis 02. C-SAM/SAT (ultrasonic scanning microscope) (1) The lattice structure, impurity particles, inclusions, and precipitates inside the material. (2) Internal cracks. (3) Layered defects. (4) Voids, bubbles, voids, etc. 03. Non destructive testing, X-Ray detects various defects in IC packaging, such as layer peeling, bursting, voids, and integrity of wiring. Possible defects in PCB manufacturing process, such as poor alignment or bridging, open circuit, short circuit, or abnormal connection defects, and integrity of solder balls in packaging. These are the first non-destructive analysis methods used after chip failure, including 2DX-Ray and 3DX-Ray. 04. SEM scanning electron microscope/EDX energy dispersion X-ray instrument (material structure analysis/defect observation, conventional micro zone analysis of element composition, precise measurement of component size). 05. Take the die and use laser and automatic acid opening machines to remove the packaging shell of the tested sample (not applicable to ceramic and metal packaging), exposing the internal structure of the tested sample. 06. OBIRCH/EMMI (Low Light Microscope/OBIRCH Laser Beam Induced Impedance Value Change Test)/Thermal Hot Spot Detection (These three are commonly used leakage current path analysis methods to find hot spots, LC needs to use a probe table, oscilloscope) 07. Cutting Sample Preparation: Use a cutting sample preparation module to fix small samples for subsequent experiments. 08. Layer removal: Use a plasma etching machine (RIE) to remove the passivation layer inside the chip, exposing the underlying metal of the tested sample. If it is necessary to remove the metal layer and observe the underlying structure, a grinder can be used to grind the layer. 09. FIB will make some circuit modifications and observe the tangency points. 10. Probe Station/Probing Test. 11. ESD/Latch up electrostatic discharge/latch utility testing (some customers conduct these two reliability tests before the chip flows into the client, and some customers only think of selecting good chips for inspection after the failure occurs) has already mentioned most commonly used methods. In addition to commonly used methods, there are also other failure analysis methods, such as atomic force microscopy (AFM), secondary ion mass spectrometry (SIMS), time of flight mass spectrometry (TOF-SIMS), transmission electron microscopy (TEM), field emission electron microscopy (FEM), field emission scanning Auger probe, X-ray photoelectron spectroscopy (XPS), L-I-V testing system, energy loss X-ray microanalysis system, and many other methods. However, these projects are not very commonly used. The above article is a partial list. For more testing needs and details, please consult the online consultant of the free consulting agency: 15201733840 (phone and WeChat). We conduct testing on the top 100 inspection websites - issuing authoritative testing reports has legal effect